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Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Active, expires Application number US14/945,329 Other versions US20170093618A1

Google Patents Logical 元 processing for L2 hardware switchesĭownload PDF Info Publication number US9979593B2 US9979593B2 US14/945,329 US201514945329A US9979593B2 US 9979593 B2 US9979593 B2 US 9979593B2 US 201514945329 A US201514945329 A US 201514945329A US 9979593 B2 US9979593 B2 US 9979593B2 Authority US United States Prior art keywords logical packet switch mac address mfe Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. Google Patents US9979593B2 - Logical 元 processing for L2 hardware switches The 40G example and the 100G example listed above are one of the few multiport high speed ToR switches with low latency and high performance.ġ0G ToR/Leaf Ethernet Switch: What Is the Right Choice?ĭata Center Architecture Design: Top of Rack vs.US9979593B2 - Logical 元 processing for L2 hardware switches 40G and 100G ToR switches that can support multiple data rates are still not many.

ToR switches are often required to be multiport and have low-latency since they have to deal with traffic in different layers.Īt present, 1G and 10G data rates still contribute to the largest portion of all switch-to-server connections.